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Rev 0; 10/06
4-Channel Cold-Cathode Fluorescent Lamp Controller
General Description
The DS3994 is a 4-channel controller for cold-cathode fluorescent lamps (CCFLs) that backlight liquid crystal displays (LCDs) in TV and PC monitor applications. The DS3994's features make it suitable for use in even the largest LCDs, while its low BOM cost makes it ideal for the entire range of LCD TVs and monitors. The DS3994 can stagger the lamp bursts from each of the four channels. This feature allows scanning backlight schemes for video quality improvement to be implemented using a single CCFL controller IC, making it very simple and inexpensive to provide this enhancement. In addition, staggering the bursts from each channel can be used to minimize current ripple on the display power supply, which is especially important for larger LCDs. The relative stagger between each of the channels is programmable, so this feature can be tailored to the specific application. The DS3994 uses a push-pull drive architecture but it can also support full and half bridge drive schemes. Contact the factory for more details.
Features
o High-Density CCFL Controller for LCD TV and PC Monitor Backlights o Programmable Staggered Start for Burst Dimming on Each Channel o Strike Frequency Boost Option o Programmable Strike Time o Can Be Easily Cascaded o Minimal External Components o Analog Brightness Control o Gate Driver Phasing Minimizes DC Supply Current Surges o Per-Channel Lamp Fault Monitoring for Lamp Open, Lamp Overcurrent, Failure to Strike, and Overvoltage Conditions o Accurate (2%) On-Board Oscillator Lamp Frequency (20kHz to 80kHz) o Wide Range On-Board DPWM Burst-Dimming Oscillator (22.5Hz to 440Hz) o Can Be Synchronized to External Sources for the Lamp and DPWM Frequencies o < 10% to 100% Dimming Range o Soft-Start Minimizes Audible Transformer Noise o I2C-Compatible Serial Port and On-Board Nonvolatile (NV) Memory Allow Device Customization o 3-Byte NV User Memory for Storage of Serial Numbers and Date Codes o 4.5V to 5.5V Single-Supply Operation o -40C to +85C Temperature Range o 28-Pin SO (300 mils) Package
DS3994
Applications
LCD Televisions LCD PC Monitors
Pin Configurations
TOP VIEW
LOSC 1 A0 2 PSYNC 3 POSC 4 BRIGHT 5 SVM 6 GA1 7 GB1 8 LCM1 9 OVD1 10 GA2 11 GB2 12 LCM2 13 OVD2 14 28 LSYNC 27 FAULT 26 SCL 25 SDA 24 OVD4
Ordering Information
PART DS3994Z+ TEMP RANGE -40C to +85C PIN-PACKAGE 28 SO-300
DS3994
23 LCM4 22 GB4 21 GA4 20 OVD3 19 LCM3 18 GB3 17 GA3 16 VCC 15 GND
+Denotes lead-free package.
Typical Operating Circuits appear at end of data sheet.
SO-300
______________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC, SDA, and SCL Relative to Ground.............................................-0.5V to +6.0V Voltage Range on Leads Other than VCC, SDA, and SCL................................-0.5V to (VCC + 0.5V), not to exceed +6.0V Operating Temperature Range ...........................-40C to +85C EEPROM Programming Temperature Range .........0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature...................See J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C.)
PARAMETER Supply Voltage Input Logic 1 Input Logic 0 SVM Voltage Range BRIGHT Voltage Range LCM Voltage Range OVD Voltage Range Gate-Driver Output Charge Loading SYMBOL VCC VIH VIL VSVM VBRIGHT VLCM VOVD QG (Note 2) (Note 2) (Note 1) CONDITIONS MIN 4.5 2.2 -0.3 -0.3 -0.3 -0.3 -0.3 TYP MAX 5.5 VCC + 0.3 0.8 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 20 UNITS V V V V V V V nC
ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to +5.5V, TA = -40C to +85C.)
PARAMETER Supply Current Input Leakage (Digital Pins) Output Leakage (SDA, FAULT) Low-Level Output Voltage (SDA, FAULT) Low-Level Output Voltage (PSYNC, LSYNC) Low-Level Output Voltage (GA, GB) High-Level Output Voltage (PSYNC, LSYNC) SYMBOL ICC IL ILO VOL1 VOL2 VOL3 VOL4 VOH1 High impedance IOL1 = 3mA IOL2 = 6mA IOL3 = 4mA IOL4 = 4mA IOH1 = -1mA VCC - 0.4 CONDITIONS GA, GB loaded with 600pF, 4 channels active -1.0 -1.0 MIN TYP 9 MAX 16 +1.0 +1.0 0.4 0.6 0.4 0.4 UNITS mA A A V V V V
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4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +4.5V to +5.5V, TA = -40C to +85C.)
PARAMETER High-Level Output Voltage (GA, GB) UVLO Threshold--VCC Rising UVLO Threshold--VCC Falling UVLO Hysteresis SVM Falling Edge Threshold SVM Hysteresis LCM and OVD Source Current LCM and OVD Sink Current LCM and OVD DC Bias Voltage LCM and OVD Input Resistance Lamp Off Threshold Lamp Overcurrent Threshold Lamp Regulation Threshold OVD Threshold Lamp Frequency Range Lamp Frequency Source Frequency Tolerance Lamp Frequency Receiver Duty Cycle DPWM Frequency Range DPWM Source Frequency Tolerance DPWM Receiver Duty Cycle DPWM Receiver Frequency Range DPWM Receiver Minimum Pulse Width BRIGHT Voltage--Minimum Brightness BRIGHT Voltage--Maximum Brightness BRIGHT Voltage--Minimum Brightness BRIGHT Voltage--Maximum Brightness Gate-Driver Output Rise/Fall Time GAn and GBn Duty Cycle VDCB RDCB VLOT VLOC VLRT VOVDT fLF:OSC fLFS:TOL fLFR:DUTY fD:OSC fDSR:TOL fDFE:DUTY fDR:OSC tDR:MIN VBMIN VBMAX VBMIN VBMAX tR/tF (Note 4) Positive slope (CR2.7 = 0) Positive slope (CR2.7 = 0) Positive slope (CR2.7 = 1) Positive slope (CR2.7 = 1) CL = 600pF (Note 5) 3.3 50 100 44 2.0 0 POSC resistor 0.1% over temperature LOSC resistor 0.1% over temperature (Note 3) (Note 3) (Note 3) (Note 3) 1.65 3.15 2.29 2.25 20 -2 40 22.5 -2 40 22.5 25 0.5 SYMBOL VOH2 VUVLOR VUVLOF VUVLOH VSVMT VSVMH 1.95 3.7 100 2.0 150 4 4 1.35 50 1.75 3.35 2.35 2.35 1.85 3.55 2.41 2.45 80 +2 60 440.0 +2 60 440.0 2.05 IOH2 = -1mA CONDITIONS MIN VCC - 0.4 4.3 TYP MAX UNITS V V V mV V mV A A V k V V V V kHz % % Hz % % Hz s V V V V ns %
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4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
I2C AC ELECTRICAL CHARACTERISTICS (See Figure 10)
(VCC = +4.5V to +5.5V, timing referenced to VIL(MAX) and VIH(MIN), TA = -40C to +85C.)
PARAMETER SCL Clock Frequency Bus Free Time Between Stop and Start Conditions Hold Time (Repeated) Start Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time Start Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Setup Time SDA and SCL Capacitive Loading EEPROM Write Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tW (Note 8) (Note 9) 20 (Note 8) (Note 8) (Note 7) (Note 6) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 30 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF ms
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +4.5V to +5.5V)
PARAMETER EEPROM Write Cycles SYMBOL CONDITIONS +70C (Note 10) MIN 50,000 TYP MAX UNITS Cycles
Note 1: All voltages are referenced to ground, unless otherwise noted. Currents into the IC are positive, out of the IC negative. Note 2: During fault conditions, the AC-coupled feedback values are allowed to be outside the Absolute Maximum Rating of the LCM or OVD pin for up to 1 second. Note 3: Voltage including the DC offset, VDCB. Note 4: This is the minimum pulse width guaranteed to generate an output burst, which will generate the DS3994's minimum burst duty cycle. This duty cycle may be greater than the duty cycle of the PSYNC input. Once the duty cycle of the PSYNC input is greater than the DS3994's minimum duty cycle, the output's duty cycle will track the PSYNC's duty cycle. Leaving PSYNC low (0% duty cycle) disables the GAn and GBn outputs in DPWM Slave mode. Note 5: This is the maximum lamp frequency duty cycle that will be generated at any of the GAn or GBn outputs. Note 6: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. Note 7: After this period, the first clock pulse can be generated. Note 8: CB--total capacitance allowed on one bus line in picofarads. Note 9: EEPROM write begins after a stop condition occurs. Note 10: Guaranteed by design.
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4-Channel Cold-Cathode Fluorescent Lamp Controller
Typical Operating Characteristics
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS3994 toc01
DS3994
ACTIVE SUPPLY CURRENT vs. TEMPERATURE
10.5 10.0 SUPPLY CURRENT (mA) 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 GATE QC = 3.5nC -40.0 22.5 TEMPERATURE (C) fLF:OSC = 64kHz DPWM = 100% 85.0 VCC = 4.5V VCC = 5.0V VCC = 5.5V
DS3994 toc02
INTERNAL FREQUENCY CHANGE vs. TEMPERATURE
0.8 FREQUENCY CHANGE (%) 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -40.0 22.5 TEMPERATURE (C) 85.0 LAMP FREQUENCY DPWM FREQUENCY
DS3994 toc03
10 9 SUPPLY CURRENT (mA) 8 DPWM = 100% 7 6 5 4 4.5 GATE QC = 3.5nC 4.7 4.9 5.1 SVM < 2V fLF:OSC = 64kHz 5.3 DPWM = 50% DPWM = 10%
11.0
1.0
SUPPLY VOLTAGE (V)
TYPICAL OPERATION AT 12V
DS3994 toc04
TYPICAL OPERATION AT 15V
DS3994 toc05
TYPICAL OPERATION AT 18V
DS3994 toc06 DS3994 toc08
10s 5.0V GA 10s 5.0V GB 10s 2.0V LCM 10s 2.0V OVD
10s 5.0V GA 10s 5.0V GB 10s 2.0V LCM 10s 2.0V OVD
10s 5.0V GA 10s 5.0V GB 10s 2.0V LCM
10s 2.0V OVD
TYPICAL STARTUP WITH SVM
5ms 2.0V SVM
DS3994 toc07
BURST DIMMING AT 150Hz AND 10%
1ms 5.0V GA 1ms 5.0V GB 1ms 2.0V LCM
5ms 5.0V GB 5ms 2.0V LCM
5ms 1.0V OVD
1ms 2.0V OVD
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4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
Typical Operating Characteristics (continued)
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
BURST DIMMING AT 150Hz AND 50%
DS3994 toc09
SOFT-START AT VINV = 18V
DS3994 toc10
LAMP STRIKE--EXPANDED VIEW
DS3994 toc11
1ms 5.0V GA 1ms 5.0V GB 1ms 2.0V LCM 1ms 1.0V OVD
20s 5.0V GA 20s 5.0V GB 20s 2.0V LCM
1ms 5.0V GA 1ms 5.0V GB 1ms 2.0V LCM 1ms 2.0V OVD
20s 1.0V OVD
LAMP STRIKE WITH OPEN LAMP AUTORETRY DISABLED
DS3994 toc12
BURST DIMMING STAGGER
2.0ms 5.0V GA1 2.0ms 5.0V GA2 2.0ms 5.0V GA3
DS3994 toc13
LAMP OUT (LAMP OPENED), AUTORETRY DISABLED
DS3994 toc14
0.55 5.0V GA 0.55 5.0V GB 0.55 2.0V LCM
0.1s 5.0V GA 0.1s 5.0V GB LAMP OPENED 0.1s 2.00V LCM 0.1s 2.00V OVD
0.55 1.0V OVD
LST0 AND LST1 = 0
2.0ms 5.0V GA4
LAMP STRIKE WITH 0% FREQUENCY BOOST
DS3994 toc15
LAMP STRIKE WITH 33% FREQUENCY BOOST
2ms 5.0V GA 2ms 2.0V LCM
DS3994 toc16
2ms 5.0V GA 2ms 2.0V LCM
2ms 0.5V OVD
2ms 0.5V OVD
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4-Channel Cold-Cathode Fluorescent Lamp Controller
Pin Description
NAME GAn GBn PINS BY CHANNEL (n = 1-4) CH 1 7 8 CH 2 11 12 CH 3 17 18 CH 4 21 22 MOSFET A Gate Drive. Connect directly to logic-level mode n-channel MOSFET. Leave open if channel is unused. MOSFET B Gate Drive. Connect directly to logic-level mode n-channel MOSFET. Leave open if channel is unused. Lamp Current Monitor Input. Lamp current is monitored by measuring a voltage across a resistor placed in series with the low-voltage side of the lamp. Leave open if channel is unused. Overvoltage Detection. Lamp voltage is monitored through a capacitordivider placed on the high-voltage side of the transformer. Leave open if channel is unused. FUNCTION
DS3994
LCMn
9
13
19
23
OVDn
10
14
20
24
NAME GND VCC BRIGHT SVM SDA SCL FAULT
PIN 15 16 5 6 25 26 27 Ground Connection Power-Supply Connection
FUNCTION
Analog Brightness Control Input. Used to control DPWM dimming. Ground when using a PWM signal at PSYNC to control brightness. Supply Voltage Monitor Input. Used to monitor the inverter voltage for undervoltage conditions. Serial Data Input/Output. I2C bidirectional data pin, which requires a pullup resistor to realize high logic levels. Serial Clock Input. I2C clock input. Fault Output. This active-low, open-drain pin, requires an external pullup resistor to realize high logic levels. Lamp Frequency Input/Output. This pin is the input for an externally sourced lamp frequency when the DS3994 is configured as a lamp frequency receiver. If the DS3994 is configured as a lamp frequency source (i.e., the lamp frequency is generated internally), the frequency is output on this pin for use by other lamp frequency receiver DS3994s. Lamp Oscillator Resistor Adjust. A resistor to ground on this pin sets the frequency of the lamp oscillator. Address Select Input. Determines the DS3994's I2C slave address. DPWM Input/Output. This pin is the input for an externally generated DPWM signal when the DS3994 is configured as a DPWM receiver. If the DS3994 is configured as a DPWM source (i.e., the DPWM signal is generated internally), the DPWM signal is output on this pin for use by other DPWM receiver DS3994s. DPWM Oscillator Resistor Adjust. A resistor to ground on this lead sets the frequency of the DPWM oscillator (dimming clock). This lead can optionally accept a 22.5Hz to 440Hz clock as the source timing for the internal DPWM signal.
LSYNC
28
LOSC A0 PSYNC
1 2 3
POSC
4
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4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
Functional Diagram
EEPROM I2C DEVICE CONFIGURATION PORT SDA SCL A0 I2CCOMPATIBLE INTERFACE CONTROL REGISTERS 3-BYTE USER MEMORY SYSTEM ENABLE/POR 2.0V SVM SUPPLY VOLTAGE MONITOR UVLO VCC [4.5V TO 5.5V]
DS3994
FAULT FAULT HANDLING CHANNEL FAULT CHANNEL ENABLE
LAMP FREQUENCY INPUT/OUTPUT LSYNC
20kHz TO 80kHz LFSS BIT AT CR1.2 x512 PLL 4-PHASE GENERATOR [20kHz TO 80kHz] FOUR INDEPENDENT CCFL CONTROLLERS [10.24MHz TO 40.96MHz]
LCMn LAMP CURRENT MONITOR
EXTERNAL RESISTOR LAMP FREQUENCY SET
LOSC
20kHz TO 80kHz OSCILLATOR (2%) DPSS BIT AT CR1.3
OVDn OVERVOLTAGE DETECTION
MUX RGSO BIT AT CR1.4
0 1 1 0 MUX DPSS BIT AT CR1.3 DPWM SIGNAL MOSFET GATE GBn DRIVERS GAn
DPWM SIGNAL INPUT/OUTPUT PSYNC
ANALOG BRIGHTNESS CONTROL BRIGHT EXTERNAL RESISTOR DPWM FREQUENCY SET/ DPWM CLOCK INPUT 0 POSC 1 22.5Hz TO 440Hz OSCILLATOR (5%) MUX POSCS BIT AT CR1.1 RAMP GENERATOR
22.5Hz TO 440Hz
GND
8
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4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
LAMP OUT 400mV CHANNEL ENABLE LAMP OVERCURRENT CHANNEL FAULT DIGITAL CCFL CONTROLLER LOC BIT IN CR1.0 LAMP STRIKE AND REGULATION 64 LAMP CYCLE INTEGRATOR OVERVOLTAGE 1.0V OVDn OVERVOLTAGE DETECTOR 1.0V GAn GBn MOSFET GATE DRIVERS 2.0V LCMn LAMP CURRENT MONITOR
DIMMING PWM SIGNAL 512 x LAMP FREQUENCY [10.24MHz ~ 40.96MHz] LAMP FREQUENCY [20kHz ~ 80kHz]
LAMP MAXIMUM VOLTAGE REGULATION
GATE DRIVERS
Figure 1. Per Channel Logic Diagram
Detailed Description
The DS3994 uses a push-pull drive scheme to convert a DC voltage (5V to 24V) to the high-voltage (600VRMS to 1200VRMS) AC waveform that is required to power the CCFLs. The push-pull drive scheme uses a minimal number of external components, which reduces assembly cost and makes the printed circuit board design easy to implement. The push-pull drive scheme also provides an efficient DC-to-AC conversion and produces near-sinusoidal waveforms. Each DS3994 channel drives two logic-level n-channel MOSFETs that are connected between the ends of a step-up transformer and ground (see Figure 1 and the Typical Operating Circuit). The transformer has a center tap on the primary side that is connected to a DC voltage supply. The DS3994 alternately turns on the two MOSFETs to create the high-voltage AC waveform on the secondary side. By varying the duration of the MOSFET turn-on times, the controller is able to accurately control the amount of current flowing through the CCFL. A resistor in series with the CCFL's ground connection enables current monitoring. The voltage across this resistor is fed to the lamp current monitor (LCM) input on the DS3994. The DS3994 compares the peak resistor voltage against an internal reference voltage to determine the duty cycle for the MOSFET gates. Each CCFL
receives independent current monitoring and control, which results in equal brightness across all of the lamps and maximizes the lamp's brightness and lifetime. The DS3994 can also drive more than one lamp per channel. See the Typical Operating Circuit section for implementation details when using multiple lamps per channel.
EEPROM Registers and I2C-Compatible Serial Interface
The DS3994 uses an I2C-compatible serial interface for communication with the on-board EEPROM configuration registers and user memory. The configuration registers, four Burst Dimming Stagger Registers (BDS1/2/3/4), and three Control Registers (CR1/2/3)--allow the user to customize many DS3994 parameters such as the time delay to stagger the burst dimming between channels, the lamp and dimming frequency sources, fault-monitoring options, and channel enabling/disabling. The three bytes of nonvolatile user memory can be used to store manufacturing data such as date codes, serial numbers, or product identification numbers. The device is shipped from the factory with the configuration registers programmed to a set of default configuration parameters. To inquire about custom factory programming, please send an email to MixedSignal.Apps@dalsemi.com.
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4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
Channel Phasing
The lamp-frequency MOSFET gate turn-on times are equally phased among the four channels during the burst period. This reduces the inrush current that would result from all lamps switching simultaneously, and hence eases the design requirements for the DC supply. Figure 2 details how the four channels are phased. Note that it is the lamp frequency signals that are phased, NOT the DPWM signals. See the Burst Dimming Stagger Functionality section for details or to adjust the DPWM signals of each channel. the DPWM cycle, the lamps are driven at the selected lamp frequency (20kHz to 80kHz) as shown in Figure 7. This part of the cycle is called the "burst" period because of the lamp frequency burst that occurs during this time. During the low period of the DPWM cycle, the controller disables the MOSFET gate drivers so the lamps are not driven. This causes the current to stop flowing in the lamps, but the time is short enough to keep the lamps from de-ionizing. Dimming is increased/ decreased by adjusting (i.e., modulating) the duty cycle of the DPWM signal. The DS3994 can generate its own DPWM signal internally (set DPSS = 0 in CR1), which can then be sourced to other DS3994s if required, or the DPWM signal can be supplied from an external source (set DPSS = 1 in CR1).
Lamp Dimming Control (DPWM)
The DS3994 uses a digital pulse-width modulated (DPWM) signal (22.5Hz to 440Hz) to provide efficient and precise lamp dimming. During the high period of
4 CHANNEL SEQUENCE
1
2
3
4
1
2
3
4
1
2
3
4
GA1 GB1
VARIABLE MOSFET GATE DUTY CYCLE
GA2 GB2
GA3 GB3
GA4 GB4
MOSFET GATEDRIVE SIGNALS AT LAMP FREQUENCY
DIMMING CLOCK (DPWM) FREQUENCY
Figure 2. Channel Phasing Detail 10 ____________________________________________________________________
4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
RESISTOR-SET DIMMING CLOCK 2.0V OR 3.3V BRIGHT 2.0V OR 3.3V BRIGHT EXTERNAL DIMMING CLOCK
ANALOG DIMMING CONTROL VOLTAGE
0.5V OR 0.0V
ANALOG DIMMING CONTROL VOLTAGE
0.5V OR 0.0V
DPWM SIGNAL 22.5Hz TO 440Hz
PSYNC (OUTPUT) POSC
DPWM SIGNAL 22.5Hz TO 440Hz EXTERNAL DIMMING CLOCK 22.5Hz TO 440Hz
PSYNC (OUTPUT) POSC
RESISTOR TO SET THE DIMMING FREQUENCY
Figure 3. DPWM Source Configuration Options
Table 1. BRIGHT Analog Dimming Input Slope and Voltage Range Configuration
CR2.7 0 0 1 1 CR3.0 0 1 0 1 RANGE 0.5 to 2V 0.5 to 2V 0 to 3.3V 0 to 3.3V SLOPE Positive Negative Positive Negative MINIMUM BRIGHTNESS 0.5V 2.0V 0V 3.3V MAXIMUM BRIGHTNESS 2.0V 0.5V 3.3V 0V
Lamp Dimming Control (DPWM)
BRIGHT
DPWM SIGNAL 22.5Hz TO 440Hz
PSYNC (INPUT)
POSC
Figure 4. DPWM Receiver Configuration
To generate the DPWM signal internally, the DS3994 requires a clock (referred to as the dimming clock) to set the DPWM frequency. The user can supply the dimming clock by setting POSCS = 1 in CR1 and applying an external 22.5Hz to 440Hz signal at the POSC pin, or DS3994's clock can be generated by the DS3994's oscillator (set POSCS = 0 in CR1), in which case the frequency is set by an external resistor at the POSC pin. These two dimming clock options are shown in Figure 3. Regardless of whether the dimming clock is generated internally or sourced externally, the POSCR1 and POSCR2 bits in CR2 must be set to match the desired dimming clock frequency.
When the DPWM signal is generated internally, its duty cycle (and, thus, the lamp brightness) is controlled by a user-applied analog voltage at the BRIGHT input. Users can select a positive or negative slope for the bright pin's dimming input as well as the voltage range. If SLOPE = 0 in CR3, then the slope is positive. This means that a BRIGHT voltage less than the minimum voltage causes the DS3994 to operate with the minimum burst duty cycle, providing the lowest brightness setting, while any voltage greater than the maximum voltage causes a 100% burst duty cycle (i.e., lamps always being driven), which provides the maximum brightness. For voltages between the minimum voltage and the maximum voltage, the duty cycle varies linearly between the minimum and 100%. The internally generated DPWM signal is available at the PSYNC I/O pin (set RGSO = 0 in CR1) for sourcing to other DS3994s, if any, in the circuit. This allows all DS3994s in the system to be synchronized to the same DPWM signal. The DS3994 that is generating the DPWM signal for other DS3994s in the system is referred to as the DPWM source.
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11
4-Channel Cold-Cathode Fluorescent Lamp Controller
When the DPWM signal is provided by an external source, either from the PSYNC pin of another DS3994 or from some other user-generated source, it is input into the PSYNC I/O pin of the DS3994. In this mode, the BRIGHT and POSC inputs are disabled and should be grounded (see Figure 4). When multiple DS3994s are used in a design, DS3994s configured to use externally generated DPWM signals are referred to as DPWM receivers.
DS3994
Burst Dimming Stagger (BDS) Functionality
The DS3994 also features burst dimming stagger (BDS) functionality integrated into the burst dimming controller. BDS is useful to reduce the current ripple on the DC supply as well as improve the visual motion response of the LCD panel. This feature allows users to enter a digital code into each channel independent register (BDS1/2/3/4) that would delay the start of each burst period. The 8-bit BDS code can be calculated by using Table 2 and the following equations.
Table 2. Multiplication Factor M, Based on Lamp Frequency Oscillator and DPWM Frequency Oscillator
M, LAMP CYCLE PERIOD MULTIPLICATION FACTOR POSCR1 (CR2.2) 0 0 1 1 POSCR0 (CR2.1) 0 1 0 1 SELECTED PWM OSCILLATOR RANGE (Hz) 22.5 to 55 45 to 110 90 to 220 180 to 440 LAMP OSCILLATOR = 40 TO 80kHz (LOFS = 0) 8 4 2 1 LAMP OSCILLATOR = 20 TO 40kHz (LOFS = 1) 8 4 2 1
BDS_Resolution =
M fLF : OSC
BDS_Delay = BDS_Resolution x BDS_8-Bit_Value
If a BDS_Delay is used that is longer than the burst period, then the gate drivers, GA and GB, have no output. For example, assume a lamp frequency of 50kHz and a burst frequency of 167Hz. The step resolution of the burst-dimming stagger would be 40s (2/50,000). To achieve equal stagger, as shown in Figure 5, the BDS1/2/3/4 registers would be programmed as described in Table 3.
BURST DIMMING CYCLE (167Hz/6ms) CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 1.5ms 3.0ms 4.5ms
Figure 5. Example Burst Dimming Stagger Cycle
Table 3. Example BDS1/2/3/4 Programmed Values
CHANNEL 1 2 3 4 REGISTER BDS1 BDS2 BDS3 BDS4 DESIRED STAGGER (ms) 0 1.5 3.0 4.5 STEP RESOLUTION (s) 40 40 40 40 COUNT 0 38 75 113 PROGRAMMED VALUE 00h 26h 48h 71h
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4-Channel Cold-Cathode Fluorescent Lamp Controller
Lamp Strike Frequency Boost
The DS3994 also features a programmable lamp strike frequency boost option. During the strike period, the transformer secondary is essentially unloaded. The lamp frequency be can be easily increased causing a higher strike voltage. The SB0/1/2 bits in CR3 control how the frequency is increased during lamp strike. A setting of 000b results in no frequency increase, while the maximum setting (111b) causes a 100% increase. Once the DS3994 detects that the lamp has struck, the lamp frequency is automatically reset to the nominal run level.
Configuring Systems with Multiple DS3994s
The source and receiver options for the lamp frequency clock and DPWM signal allow multiple DS3994s to be synchronized in systems requiring more than four lamps. The lamp and dimming clocks can either be generated on board the DS3994 using external resistors to set the frequency, or they can be sourced by the host system to synchronize the DS3994 to other system resources. Figure 6 shows various multiple DS3994 configurations that allow both lamp and/or DPWM synchronization for all DS3994s in the system.
DS3994
Lamp Frequency Configuration
The DS3994 can generate its own lamp frequency clock internally (set LFSS = 0 in CR1), which can then be sourced to other DS3994s if required, or the lamp clock can be supplied from an external source (set LFSS = 1 in CR1). When the lamp clock is internally generated, the frequency (20kHz to 80kHz) is set by an external resistor at the LOSC. In this case, the DS3994 can act as a lamp frequency source because the lamp clock is output at the LSYNC I/O pin for synchronizing any other DS3994s configured as lamp frequency receivers. The DS3994 acts as a lamp frequency receiver when the lamp clock is supplied externally. In this case, a 20kHz to 80kHz clock must be supplied at the LSYNC I/O. The external clock can originate from the LSYNC I/O of a DS3994 configured as a lamp frequency source or from some other source. The LOFS bit in CR3 must be set to match the appropriate lamp frequency range. If a 20kHz to 40kHz frequency is used, then LOFS must be set to 1; if a 40kHz to 80kHz frequency is used, then LOFS must be set to 0.
DPWM Soft-Start
At the beginning of each lamp burst, the DS3994 provides a soft-start that slowly increases the MOSFET gate-driver duty cycle (see Figure 7). This minimizes the possibility of audible transformer noise that could result from current surges in the transformer primary. The soft-start length is fixed at 16 lamp cycles.
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13
4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
ANALOG BRIGHTNESS 0.5V OR 0.0V RESISTOR-SET DIMMING FREQUENCY RESISTOR-SET LAMP FREQUENCY 2.0V OR 3.3V ANALOG BRIGHTNESS BRIGHT PSYNC LSYNC POSC LOSC BRIGHT PSYNC 0.5V OR 0.0V 2.0V OR 3.3V
BRIGHT PSYNC LSYNC POSC LOSC BRIGHT
DS3994
LAMP FREQUENCY SOURCE DPWM SOURCE
LAMP CLOCK (20kHz TO 80kHz) RESISTOR-SET DIMMING FREQUENCY
DS3994
LAMP FREQUENCY RECEIVER DPWM SOURCE
DS3994
PSYNC
DS3994
LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LOSC
LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LOSC
ANALOG BRIGHTNESS 0.5V OR 0.0V DIMMING CLOCK (22.5Hz TO 440Hz) RESISTOR-SET LAMP FREQUENCY
2.0V OR 3.3V
BRIGHT PSYNC LSYNC POSC LOSC BRIGHT PSYNC
ANALOG BRIGHTNESS 0.5V OR 0.0V
2.0V OR 3.3V
BRIGHT PSYNC LSYNC POSC LOSC BRIGHT
DS3994
LAMP FREQUENCY SOURCE DPWM SOURCE
LAMP CLOCK (20kHz TO 80kHz) DIMMING CLOCK (22.5Hz TO 440Hz)
DS3994
LAMP FREQUENCY RECEIVER DPWM SOURCE
DS3994
PSYNC
DS3994
LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LOSC
LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LOSC
DPWM SIGNAL (22.5Hz TO 440Hz)
BRIGHT PSYNC LSYNC POSC
DPWM SIGNAL (22.5Hz TO 440Hz)
BRIGHT PSYNC LSYNC POSC LOSC BRIGHT
DS3994
LAMP FREQUENCY SOURCE DPWM RECEIVER LAMP CLOCK (20kHz TO 80kHz)
DS3994
LAMP FREQUENCY RECEIVER DPWM RECEIVER
RESISTOR-SET LAMP FREQUENCY
LOSC BRIGHT PSYNC
DS3994
PSYNC
DS3994
LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LOSC
LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LOSC
Figure 6. Frequency Configuration Options for Designs Using Multiple DS3994s
14
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4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
DPWM SIGNAL 22.5Hz TO 440Hz
LAMP CURRENT
SOFT-START SOFT-START (EXPANDED) LAMP CYCLE GAn/GBn MOSFET GATE DRIVERS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SOFT-START PROFILE WITH INCREASING MOSFET PULSE WIDTHS OVER A 16 LAMP CYCLE PERIOD RESULTS IN A LINEAR RAMP IN LAMP CURRENT.
LAMP CURRENT
Figure 7. Digital PWM Dimming and Soft-Start
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15
4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
Setting the Lamp and Dimming Clock (DPWM) Frequencies Using External Resistors
Both the lamp and dimming clock frequencies can be set using external resistors. The resistance required for either frequency can be determined using the following formula: ROSC = K fOSC
R1 2.0V VINV
R2 SVM
DS3994
where K = 1600k*kHz for lamp frequency calculations. When calculating the resistor value for the dimming clock frequency, K will be one of four values as determined by the desired frequency and the POSCR0 and POSCR1 bit settings as shown in the Control Register 2 (CR2) in the Detailed Register Descriptions section. Example: Selecting the resistor values to configure a DS3994 to have a 50kHz lamp frequency and a 160Hz dimming clock frequency: For this configuration, POSCR0 and POSCR1 must be programmed to 1 and 0, respectively, to select 90Hz to 220Hz as the dimming clock frequency range. This sets K for the dimming clock resistor (RPOSC) calculation to 4k*kHz. For the lamp frequency resistor (RLOSC) calculation, K = 1600k*kHz, which allows the lamp frequency K value regardless of the frequency. The formula above can now be used to calculate the resistor values for RLOSC and RPOSC as follows: RLOSC = 1600k * kHz = 32k, 50kHz 4k * kHz = 25.0k RPOSC = 0.160kHz
EXAMPLE: R1 = 10k, R2 = 40k SETS AN SVM TRIP POINT OF 10V.
Figure 8. Setting the SVM Threshold Voltage
problems. Proper use of the SVM can prevent these problems. If desired, the SVM can be disabled by connecting the SVM pin to VCC. R + R2 VTRIP = 2.0 1 R1 The VCC monitor is used as a 5V supply undervoltage lockout (UVLO) that prevents operation when the DS3994 does not have adequate voltage for its analog circuitry to operate or to drive the external MOSFETs. The VCC monitor features hysteresis to prevent VCC noise from causing spurious operation when VCC is near the trip point. This monitor cannot be disabled by any means.
Supply Monitoring
The DS3994 monitors both the transformer's DC supply and its own VCC supply to ensure that both voltage levels are adequate for proper operation. The inverter's transformer supply (VINV) is monitored using an external resistor-divider that is the input into a comparator (see Figure 8) with a 2V threshold. Using the equation below to determine the resistor values, the supply voltage monitor (SVM) trip point (VTRIP) can be customized to shut off the inverter when the transformer's input voltage drops below any specified value. Operating with the transformer's supply at too low of a level can prevent the inverter from reaching the strike voltage and could potentially cause numerous other
Fault Monitoring
The DS3994 provides extensive fault monitoring for each channel. It can detect open-lamp, lamp overcurrent, failure to strike, and overvoltage conditions. The DS3994 can be configured to disable all channels if one or more channels enter a Fault State, or it can be configured to disable only the channel where the fault occurred. Once a Fault State has been entered, the FAULT output is asserted and the channel(s) remain disabled until either the DS3994 is power-cycled or the inverter's DC supply is power-cycled. The DS3994 can also be configured to automatically attempt to clear a detected fault (except lamp overcurrent) by restriking the lamp, as explained in Step 4. Configuration bits for the fault monitoring options are located in the control registers.
16
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4-Channel Cold-Cathode Fluorescent Lamp Controller
Figure 9 shows a flowchart of how the DS3994 controls and monitors each lamp. The steps are as follows: 1) Supply Check--The lamps will not turn on unless the DS3994 supply voltage is 4.5V and the voltage at the supply voltage monitor (SVM) input is 2V. 2) Strike Lamp--When both the DS3994 and the DC inverter supplies are above these minimum values, the DS3994 attempts to strike each enabled channel. The DS3994 slowly ramps up the MOSFET gate duty cycle until the lamp strikes. The controller detects that the lamp has struck by detecting current flow in the lamp. If during the strike ramp the maximum allowable voltage is reached, the controller stops increasing the MOSFET gate duty cycle to keep from overstressing the system. The DS3994 goes into a fault handling state (step 4) if the lamp has not struck after the timeout period as defined by the LST0 and LST1 control bits in the CR3 register. If an overvoltage event is detected during the strike attempt, the DS3994 disables the MOSFET gate drivers and goes into the fault handling state. 3) Run Lamp--Once the lamp is struck, the DS3994 moves to the Run Lamp stage. In the Run Lamp stage, the DS3994 adjusts the MOSFET gate duty cycle to optimize the lamp current. The gate duty cycle is always constrained to keep the system from exceeding the maximum allowable lamp voltage. If lamp current ever drops below the Lamp Out reference point for the period as defined by the LST0 and LST1 control bits in the CR3 register, then the lamp is considered extinguished. In this case the MOSFET gate drivers are disabled and the device moves to the fault handling stage. 4) Fault Handling--During fault handling, the DS3994 performs an optional (user-selectable) automatic retry to attempt to clear all faults except a lamp overcurrent. The automatic retry makes 14 additional attempts to rectify the fault before declaring the channel in a Fault State and permanently disabling the channel. Between each of the 14 attempts, the controller waits 1024 lamp cycles. In the case of a lamp overcurrent, the DS3994 instantaneously declares the channel to be in a Fault State and permanently disables the channel. The DS3994 can be configured to disable all channels if one or more channels enters a Fault State or it can be configured to disable only the channel where the fault occurred. Once a Fault State is entered, the channel remains in that state until one of the following occurs: * VCC drops below the UVLO threshold. * The SVM threshold is crossed. * The channel is disabled.
DS3994
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17
4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
DEVICE AND INVERTER SUPPLIES AT PROPER LEVELS? YES RESET FAULT COUNTER AND FAULT OUTPUT YES FAULT WAIT [1024 LAMP CYCLES] NO FAULT COUNTER = 15? YES FAULT STATE [ACTIVATE FAULT OUTPUT]
NO AUTO RETRY ENABLED? [ARD BIT AT CR1.5]
INCREMENT FAULT COUNTER
STRIKE LAMP [RAMP AND REGULATE TO OVD THRESHOLD]
LAMP STRIKE TIMEOUT [SEE REGISTER CR3]
IF LAMP REGULATION THRESHOLD IS MET
OVERVOLTAGE [64 LAMP CYCLES]
LAMP OVERCURRENT [INSTANTANEOUS IF ENABLED VIA THE LOC BIT AT CR1.0]
RUN LAMP [REGULATE LAMP CURRENT BOUNDED BY LAMP VOLTAGE]
LAMP OUT TIMEOUT [SEE REGISTER CR3]
MOSFET GATE DRIVERS ENABLED
Figure 9. Fault-Handling Flow Chart
18
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4-Channel Cold-Cathode Fluorescent Lamp Controller
Detailed Register Descriptions
The DS3994's register map is shown in Table 4. Detailed register and bit descriptions follow in the subsequent tables.
DS3994
Table 4. Register Map
BYTE ADDRESS F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FD-FFh BYTE NAME Reserved Reserved Reserved Reserved CR1 CR2 Reserved Reserved BDS1 BDS2 BDS3 BDS4 CR3 User Memory FACTORY DEFAULT* 21h 43h 65h 77h 20h 08h 00h 00h 00h 00h 00h 00h 00h 00h DPD BVRS -- -- FRS LD1 -- -- BIT 7 BIT 6 -- -- -- -- ARD LD0 -- -- RGSO 0 -- -- DPSS 1 -- -- LFSS POSCR1 -- -- BIT 5 BIT 4 BIT 3 BIT 2 -- -- -- -- POSCS POSCR0 -- -- LOC UMWP -- -- BIT 1 BIT 0
Burst dimming stagger for channel 1. Burst dimming stagger for channel 2. Burst dimming stagger for channel 3. Burst dimming stagger for channel 4. LOFS EE IGO EE SB2 EE SB1 EE SB0 EE LST1 EE LST0 EE SLOPE EE
*This is the factory-programmed default stored in EEPROM.
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19
4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
F4h: Control Register 1 (CR1)
BIT 0 NAME LOC Lamp Overcurrent 0 = Lamp overcurrent detection disabled. 1 = Lamp overcurrent detection enabled. FUNCTION
1
POSC Select. See POSCR0 and POSCR1 bits in Control Register 2 to select the oscillator range. POSCS 0 = Connect POSC to ground with a resistor to set the dimming frequency. 1 = Connect POSC to an external 22.5Hz to 440Hz dimming clock to set the dimming frequency. Lamp Frequency Source Select 0 = Lamp frequency source mode. The lamp frequency is generated internally and sourced at the LSYNC output for use by lamp frequency receivers. 1 = Lamp frequency receiver mode. The lamp frequency must be provided at the LSYNC input. DPWM Signal Source Select 0 = DPWM source mode. DPWM signal is generated internally, and can be output at PSYNC pin (see RGSO bit). 1 = DPWM receiver mode. DPWM signal is generated externally and supplied at the PSYNC input. Ramp Generator Source Option 0 = Sources DPWM at the PSYNC output. 1 = Sources the internal ramp generator at PSYNC output. Autoretry Disable 0 = Autoretry function enabled. 1 = Autoretry function disabled. Fault Response Select 0 = Disable only the malfunctioning channel. 1 = Disable all channels upon fault detection at any channel. DPWM Disable 0 = DPWM function enabled. 1 = DPWM function disabled. DPWM set to 100% duty cycle.
2
LFSS
3
DPSS
4
RGSO
5
ARD
6
FRS
7
DPD
20
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4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
F5h: Control Register 2 (CR2)
BIT 0 NAME UMWP User Memory Write Protect 0 = User Memory Write Access Blocked 1 = User Memory Write Access Permitted FUNCTION
1
POSCR0
DPWM Oscillator Range Select. When using an external source for the dimming clock, these bits must be set to match the external oscillator's frequency. When using a resistor to set the dimming frequency, these bits plus the external resistor control the frequency. POSCR1 POSCR0 0 1 0 1 DIMMING CLOCK (DPWM) FREQUENCY RANGE (Hz) 22.5 to 55.0 45 to 110 90 to 220 180 to 440 Reserved. Should be set to one. Reserved. Should be set to zero. Lamp Disable. Used to disable channels if all 4 are not required for an application. K (k-kHz) 1 2 4 8
2
POSCR1
0 0 1 1
3 4
Reserved Reserved
5
LD0
LD1 0 0 1 1
LD0 0 1 0 1
CHANNELS DISABLED All Channels Enabled 4 2/4 1/2/4
NUMBER OF ACTIVE LAMP CHANNELS 4 3 2 1
6
LD1
7
BVRS
Bright Voltage Range Select. 0 = 0.5V to 2.0V 1 = 0.0V to 3.3V
F8-FBh: Burst Dimming Stagger (BDS1/2/3/4)
BIT 0 1 2 3 4 5 6 7 NAME BDSC0 BDSC1 BDSC2 BDSC3 BDSC4 BDSC5 BDSC6 BDSC7 8-Bit Programmable Counter That Staggers the Start of Burst Dimming. 00h = 0ms stagger. Setting the stagger longer than the burst dimming cycle results in the channel never turning on. See Table 2. FUNCTION
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21
4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
FCh: Control Register 3 (CR3)
BIT 0 NAME SLOPE BRIGHT Analog Dimming Slope Select 0 = Positive Slope 1 = Negative Slope STRIKE AND LAMP OUT TIMEOUT IN LAMP FREQUENCY CYCLES LST1 1 LST0 0 0 2 LST1 1 1 0 1 0 1 LST0 LAMP OSCILLATOR = 40kHz TO 80kHz (LOFS = 0) 32,768 65,536 98,304 131,072 LAMP OSCILLATOR = 20kHz TO 40kHz (LOFS = 1) 16,384 32,768 49,152 65,536 FUNCTION
EXAMPLE TIME OUT IF LAMP FREQUENCY IS 25kHz OR 50kHz
0.66 seconds 1.31 seconds 1.97 seconds 2.62 seconds
Note: The strike frequency boost does not affect this timeout. LAMP STRIKE FREQUENCY BOOST SELECT 3 SB0 SB2 0 0 4 SB1 0 0 1 1 5 SB2 1 1 6 IGO SB1 0 0 1 1 0 0 1 1 SB0 0 1 0 1 0 1 0 1 LAMP STRIKE FREQUENCY BOOST 0% 14% 23% 33% 46% 60% 78% 100% EXAMPLE STRIKE FREQUENCY IF LAMP FREQUENCY IS 50kHz 50kHz 57kHz 61.5kHz 66.7kHz 73kHz 80kHz 89kHz 100kHz
Invert MOSFET Gate A and Gate B Driver Outputs 0 = Do not invert GA and GB outputs. 1 = Invert GA and GB outputs. Lamp Oscillator Frequency Select 0 = 40kHz to 80kHz 1 = 20kHz to 40kHz
7
LOFS
22
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4-Channel Cold-Cathode Fluorescent Lamp Controller
I2C Definitions
The following terminology is commonly used to describe I2C data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start, and stop conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states. Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See the timing diagram for applicable timing. Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition. See the timing diagram for applicable timing. Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition. See the timing diagram for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (see Figure 10). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (see Figure 10) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An acknowledgement (ACK) or not acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 10) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data.
DS3994
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 10. I2C Timing Diagram ____________________________________________________________________ 23
4-Channel Cold-Cathode Fluorescent Lamp Controller
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgement is read using the bit-read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave addressing byte sent immediately following a start condition. The slave address byte (Figure 11) contains the slave address in the most significant seven bits and the R/W bit in the least significant bit. The DS3994's slave address is 101000A0 (binary), where A 0 is the value of the address pin (A 0 ). The address pin allows the device to respond to one of two possible slave addresses. By writing the correct slave address with R/W = 0, the master writes data to the slave. If R/W = 1, the master reads data from the slave. If an incorrect slave address is written, the DS3994 will assume the master is communicating with another I2C device and ignore the communications until the next start condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
DS3994
7-BIT SLAVE ADDRESS
1
0
1
0
0
0 A0
R/W
MOST SIGNIFICANT BIT
A0 PIN VALUE
DETERMINES READ OR WRITE
Figure 11. DS3994's Slave Address Byte
I2C Communication
Writing a Data Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a stop condition. Remember the master must read the slave's acknowledgement during all byte write operations. See Figure 12 for more detail. Acknowledge Polling: Any time EEPROM is written, the DS3994 requires the EEPROM write time (tW) after the stop condition to write the contents to EEPROM. During the EEPROM write time, the DS3994 will not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeatedly addressing the DS3994, which allows the next byte of data to be written as soon as the DS3994 is ready to receive the data. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to write again to the DS3994. EEPROM Write Cycles: The number of times the DS3994's EEPROM can be written before it fails is specified in the Nonvolatile Memory Characteristics table. This specification is shown at the worst-case write temperature. The DS3994 is typically capable of handling many additional write cycles when the writes are performed at room temperature. Reading a Data Byte from a Slave: To read a single byte from the slave the master generates a start condition, writes the slave address byte with R/W = 0, writes the memory address, generates a repeated start condition, writes the slave address with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. See Figure 12 for more detail.
24
____________________________________________________________________
4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
COMMUNICATIONS KEY S START A ACK NOT ACK X X X X X WHITE BOXES INDICATE THE MASTER IS CONTROLLING SDA SHADED BOXES INDICATE THE SLAVE IS CONTROLLING SDA X X X 8-BITS ADDRESS OR DATA NOTES 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
P
STOP REPEATED START
N
2) THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT.
SR
WRITE A SINGLE BYTE S 10 1 00 0 A0 0 A MEMORY ADDRESS A DATA A P
READ A SINGLE BYTE S 10 1 00 0 A0 0 A MEMORY ADDRESS A SR 10 1 00 0 A0 1 A DATA N P
Figure 12. I2C Communications Examples
Applications Information
Addressing Multiple DS3994s On a Common I2C Bus
Each DS3994 responds to one of two possible slave addresses based on the state of the address input (A0). For information about device addressing see the I2C Communications section.
Component Selection
External component selection has a large impact on the overall system performance and cost. The two most important external components are the transformers and n-channel MOSFETs. The transformer should be able to operate in the 20kHz to 80kHz frequency range of the DS3994, and the turns ratio should be selected so the MOSFET drivers run at 28% to 35% duty cycle during steady state operation. The transformer must be able to withstand the high open-circuit voltage that will be used to strike the lamp. Additionally, its primary/secondary resistance and inductance characteristics must be considered because they contribute significantly to determining the efficiency and transient response of the system. Table 5 shows a transformer specification that has been utilized for a 12V inverter supply, 438mm x 2.2mm lamp design. The n-channel MOSFET must have a threshold voltage that is low enough to work with logic-level signals, a low on-resistance to maximize efficiency and limit the nchannel MOSFET's power dissipation, and a breakdown voltage high enough to handle the transient. The breakdown voltage should be a minimum of 3x the inverter voltage supply. Additionally, the total gate charge must be less than QG, which is specified in the Recommended DC Operating Conditions table. These specifications are easily met by many of the dual nchannel MOSFETs now available in SO-8 packages. Table 6 lists suggested values for the external resistors and capacitors used in the typical operating circuit.
25
Power-Supply Decoupling
To achieve best results, it is recommended that each VCC pin is decoupled with a 0.01F or a 0.1F capacitor to GND. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins to minimize trace inductance.
Setting the RMS Lamp Current
Resistor R8 in the typical operating circuit (Figure 13) sets the lamp current. R8 = 140 corresponds to a 5mARMS lamp current as long as the current waveform is approximately sinusoidal. The formula to determine the resistor value for a given sinusoidal lamp current is: 1 2 x ILAMP(RMS)
R8 =
____________________________________________________________________
4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
Table 5. Transformer Specifications
PARAMETER Turns Ratio (Secondary/Primary) Frequency Output Power Output Current Primary DCR Secondary DCR Primary Leakage Secondary Leakage Primary Inductance Secondary Inductance Center Tap Voltage Secondary Output Voltage 100ms minimum Continuous 10.8 2000 1000 Center tap to one end 5 200 500 12 185 70 500 12 13.2 CONDITIONS (Notes 1, 2, 3) 40 MIN TYP 40 80 6 8 kHz W mA m H mH H mH V VRMS MAX UNITS
Note 1: Primary should be Bifilar wound with center tap connection. Note 2: Turns ratio is defined as secondary winding divided by the sum of both primary windings. Note 3: 40:1 is the nominal turns ratio for driving a 438mm x 2.2mm lamp with a 12V supply. Refer to Application Note 3375 for more information.
Table 6. Resistor and Capacitor Selection Guide
DESIGNATOR R1 R2 R3 R4 R5 R6 R7 R8 C1 C2 C3 C4 C5 QTY 1 1 1 1 1 1 1 1/Ch 1/Ch 1/Ch 1/Ch 1/Ch 1 VALUE 10k 12.5k to 105k 20k to 40k 18k to 45k 4.7k 4.7k 4.7k 140 100nF 10pF 27nF 33F 0.1F TOLERANCE (%) AT 25C 1 1 1 1 5 5 5 1 10 5 5 20 10 TEMPERATURE COEFFICIENT -- -- 153ppm/C 153ppm/C Any grade Any grade Any grade -- X7R 1000ppm/C X7R Any grade X7R -- See the Setting the SVM Threshold Voltage section. 2% or less total tolerance. See the Lamp Frequency Configuration section to determine value. 2% or less total tolerance. See the Lamp Frequency Configuration section to determine value. -- -- -- See the Setting the RMS Lamp Current section. Capacitor value will also affect LCM bias voltage during power-up. A larger capacitor may cause a longer time for VDCB to reach its normal operating level. 2kV to 4kV breakdown voltage required. Capacitor value will also affect LCM bias voltage during power-up. A larger capacitor may cause a longer time for VDCB to reach its normal operating level. -- Place close to VCC and GND on DS3994. NOTES
26
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4-Channel Cold-Cathode Fluorescent Lamp Controller
Typical Operating Circuits
SUPPLY VOLTAGE (5V 10% TO 24V 10%) C5 C4
DS3994
VCC = 5V 10%
R2
ANALOG BRIGHTNESS EXTERNAL DIGITAL PWM INPUT/ INTERNAL DIGITAL PWM OUTPUT EXTERNAL LAMP FREQUENCY INPUT/ INTERNAL LAMP FREQUENCY OUTPUT
BRIGHT PSYNC LSYNC LOSC POSC
VCC SVM R1 DUAL POWER MOSFET TRANSFORMER CCFL LAMP GAn C2 C3 GBn R8
DS3994
VCC R3 R4 R5 R6 R7 FAULT LCMn CONFIGURATION PORT SDA SCL A0 GND C1 LAMP CURRENT MONITOR OVDn LAMP VOLTAGE MONITOR
NOTE 1: ONLY ONE CHANNEL SHOWN TO SIMPLIFY DRAWING. NOTE 2: SEE THE COMPONENT SELECTION SECTION FOR RECOMMENDED EXTERNAL COMPONENTS.
Figure 13. Typical Operating Circuit
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27
4-Channel Cold-Cathode Fluorescent Lamp Controller DS3994
Typical Operating Circuits (continued)
DEVICE SUPPLY VOLTAGE (5V 10%) R2 SVM ON = OPEN OFF/RESET = CLOSED R1 BULK POWER SUPPLY CAPACITANCE INVERTER SUPPLY VOLTAGE (12V 10% TO 24V 10%)
DS3994
ANALOG BRIGHTNESS DPWM SIGNAL INPUT/OUTPUT LAMP FREQUENCY INPUT/OUTPUT BRIGHT PSYNC LSYNC LOSC
VCC GND 1 OF 4 CHANNELS DUAL N-CHANNEL POWER MOSFET
GA POSC R3 R4 GB FAULT 4.7k CONFIGURATION PORT 4.7k SDA SCL A0 +12V TO +24V
+5V
CH CCFL LAMP A RFB
CL
CH CCFL LAMP B RFB LCM
CL
CH LM339 CL RFB CCFL LAMP C
CH CCFL LAMP D RFB
CL OVD
Figure 14. Typical Operating Circuit with Multiple Lamps per Channel
Chip Information
TRANSISTOR COUNT: 53,000 SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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